The present invention relates to semiconductor devices, and more particularly to semiconductor devices that are formed in a thin film of semiconductor material that sits atop an insulating layer, such as Silicon-on-Insulator (SOI) or Silicon-on-Sapphire (SOS) semiconductor devices.
Thin film, co-planar integrated circuits employing silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS technology typically include a semiconductor (silicon) layer, which is disposed atop a substrate-supported dielectric (silicon dioxide) layer, with the side wall perimeter of the devices bounded by an air or (oxide) dielectric layer. The air or oxide dielectric layer helps provide lateral isolation between adjacent devices.
This semiconductor structure typically includes a body/channel region disposed between and immediately contiguous with respective source and drain regions. Overlying the channel/body region and extending onto the surrounding support substrate is a doped polysilicon gate layer, which is insulated from the semiconductor material by a thin dielectric layer (e.g., gate oxide). The air or oxide dielectric layer that bounds the side wall perimeter of the device typically extends under the polysilicon gate layer and forms the side wall of the channel/body region. To reduce the resistivity of the polysilicon gate layer and the source and drain regions, a silicide layer is often provided over the polysilicon gate, and over the source and drain regions.
A disadvantage of many SOI transistors is the lack of a bulk silicon or body contact to the MOS transistor. If the channel/body region is left "floating", various hysteresis effects can prevent proper circuit operation. These effects include the so-called "kink" effect and the parasitic lateral bipolar action. The "kink" effect originates from impact ionization. For example, when an N-channel SOI/SOS MOSFET operates at a relatively large drain-to-source voltage, channel electrons with sufficient energy cause impact ionization near the drain end of the channel. The generated holes build up in the channel/body region of the device, thereby raising the body potential. The increased body potential reduces the threshold voltage of the MOSFET, which increases the MOSFET current and causes the so-called "kink" in the MOSFET current vs. voltage (I-V) curves.
If the impact ionization results in a large number of holes, the body bias may be raised sufficiently so that the source to body p-n junction is forward biased. The resulting emission of minority carriers into the channel/body region may cause a parasitic NPN bipolar transistor between the source, body and drain to turn on, leading to loss of gate control over the MOSFET current.
Both the "kink" effect and the parasitic bipolar effect can be avoided if charge is not allowed to accumulate in the channel/body region. A body contact is often used to extract the charge collected in the body/channel region. Because the hole charge in the channel/body region will move to lower potential regions, the body contact and the source terminals can be tied together to eliminate the "floating body" effects.
Another limitation of many SOI devices is that the side walls of the channel/body region, which are often bounded by an oxide dielectric layer, can be susceptible to inversion in the presence of ionizing radiation. Thus, there is a danger that a leakage path or `parasitic` channel may be induced along the side walls of the body/channel region, and in particular, between the source and drain. This can result in significant current leakage, even when the device is tuned off. In addition, if the manufacturing process cannot accurately control the channel doping and/or the electrostatic charge build-up along the side walls of the device, significant current leakage can occur.
FIG. 1 shows a typical prior art N-channel SOI MOSFET with body control. The MOSFET is generally shown at 8, and is commonly called a T-gate MOSFET because of the T-shape of gate 14. The T-gate MOSFET 8 has an active region 10 formed on an insulating layer and surrounded by an isolation region 12. The active region 10 is divided into three regions by T-gate 14, including the source region 20, the drain region 22 and the body-tie region 24. Typically, the T-gate 14 includes a first leg 16 and a second leg 18. The N-type source/drain regions 20 and 22 are located on either side of the first leg 16 and along the lower side of the second leg 18. A P-type body tie region 24 is located above the second leg 18. Located under the first and second legs 16 and 18 is a p-type body/channel region.
The active region 10 and isolation region 12 are provided using known techniques. A thin gate oxide layer is provided over the active region 10, followed by a doped polysilicon gate layer. The doped polysilicon gate layer and the gate oxide layer are selectively etched to form the T-shaped gate 14. The source and drain regions 20 and 22 are then selectively doped with an N-type dopant (for an N-channel device). A mask, such as mask 30, is used to define the area that is to be exposed to the N-type dopant. Likewise, the body tic region 24 is selectively doped with a P-type dopant. Finally, the source region 20, the drain region 22, the body tic region 24, and the gate 14 are each covered with a silicide layer to reduce the resistance thereof.
The T-gate configuration has a number of advantageous. First, the T-gate configuration provides a body tic connection to the body/channel region under gate 14. Thus, holes that are generated in the body/channel region under the first leg 16 of gate 14, pass through the P-type region under the second leg 18, and arrive at the P-type body tieregion 24 where they are collected by the body tie contact 26. Thus, the T-gate configuration may reduce or eliminate the substrate floating effects discussed above.
Another advantage of the T-gate configuration is that the second leg 18 eliminates the channel/dielectric interface along the upper side wall 32 of the body/channel region under the first leg 16. Accordingly, the chance that a parasitic channel will be formed along the upper side wall 32 due to ionizing radiation is reduced or eliminated. The second leg 18 also functions to prevent the silicide layer from connecting the body tieregion 24 and the source region 20 and drain region 22.
A limitation of the T-gate configuration is that the channel/dielectric interface along the lower side wall 34 of the channel remains. Thus, there is still a danger that a leakage path or "parasitic" channel may be induced along the lower side wall 34 when exposed to ionizing radiation. As indicated above, this can result in significant current leakage when the device is turned off.
Another limitation of the T-gate configuration is that a separate body tie region 24 and body tie contact 26 must be provided. Most manufacturing processes have minimum spacing requirements including poly-to-contact and contact-to-field spacings. These minimum spacing requirements often result in a substantial distance between the second leg 18 and the upper edge of the active region 10, thereby reducing the packing density that can be achieved for the device. Finally, one or more metal routes must typically be provided to the body tie contact 26. These metal routes may further reduce the packing density that can be achieved by increasing congestion on the metal layer.
Another limitation of the T-gate configuration is that the lateral pitch for two adjacent transistors must typically be relatively large. To illustrate this, a second T-gate transistor is shown at 48. Because the second leg 18 must extend beyond both the left and right edges of the active region 10, each transistor must be provided in a separate active region. This alone reduces the packing density that can be achieved for the device. In addition, however, most manufacturing processes have minimum spacing requirements including poly-enclosure-of-field 40 and poly-to-poly spacing 42. These minimum spacing requirements can also significantly increase the minimum lateral pitch of two adjacent T-gate transistors.
Finally, it is recognized that the second leg 18 of the T-gate 14 increases the gate area of each transistor. The additional gate area increases the capacitance of gate 14, which reduces the speed of the device. The additional gate area also increases the thin gate oxide area, which can reduce the overall yield of the device.
FIG. 2 shows another prior art N-channel SOI MOSFET with body control. The MOSFET is generally shown at 50, and is often referred to as an H-gate MOSFET because of the H-shape of gate 51. The H-gate MOSFET 50 is similar to the T-gate MOSFET of FIG. 1, but further includes a third leg 52 along the bottom of the source and drain regions 54 and 56. An advantage of the H-gate configuration is that the third leg 52 helps eliminate the channel/dielectric interface along the lower side wall 70 of the body/channel region under the first leg 60. As such, the chance that a parasitic channel will be formed along the lower side wall 70 due to ionizing radiation is reduced. The third leg 52 also functions to prevent the suicide layer from connecting the body tie region 66 to the source region 54 and the drain region 56.
Holes generated in the body/channel region under first leg 60 may pass through the P-type region under the second leg 58, and arrive at the P-type body tie region 62 where they are collected by the body tie contact 64. The holes may also pass through the P-type region under the third leg 52, and arrive at the P-type body tie region 66, where they are collected by the body tic contacts 68. Because there are two parallel paths from the body/channel region to body tie contacts, the resistance from the body tie contacts to the body/channel region is effectively halved relative to the T-gate configuration discussed above. This allows the body/channel region to be about twice as long as the T-gate configuration of FIG. 1 while affording the same level of protection.
A limitation of the H-gate configuration is that body contacts must be provided either above the second leg 58 or below the third leg 52, or both. Since most manufacturing processes have minimum spacing requirements including poly-to-contact and contact-to-field spacings, a substantial space may be required between the second leg 58 and the upper edge of the active region or between the third leg 52 and the bottom edge of the active region, or both. Furthermore, one or more metal routes must typically be provided to the upper body contact 64 and/or the lower body contacts 68. Both of these may reduce the packing density that can be achieved.
Another limitation of the H-gate configuration is that the additional gate area of the third leg 52 increases the capacitance of the gate 51, which as described above, can reduce the speed of the device. In addition, the additional gate area of the third leg 52 increases the thin gate oxide area, which can reduce the overall yield of the device.